SI4922DY |
RFQ for SI4922DY Required Field |
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| Product | Manufacturers | Pack | D/C |
| SI4922DY | - | 2006 | 50000 |
The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device.
Features |
| • N-Channel Vertical DMOS• Macro Model (Subcircuit Model)• Level 3 MOS• Apply for both Linear and Switching Application• Accurate over the −55 to 125°C Temperature Range• Model the Gate Charge, Transient, and Diode Reverse RecoveryCharacteristics |
